<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Roce on Le Site de François</title><link>https://lesitedefrancois.be/en/tags/roce/</link><description>Recent content in Roce on Le Site de François</description><generator>Hugo -- gohugo.io</generator><language>en</language><copyright>© 2026 François</copyright><atom:link href="https://lesitedefrancois.be/en/tags/roce/index.xml" rel="self" type="application/rss+xml"/><item><title>NCCL (NVIDIA Collective Communications Library)</title><link>https://lesitedefrancois.be/en/ai/nccl/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://lesitedefrancois.be/en/ai/nccl/</guid><description>&lt;p&gt;&lt;strong&gt;NCCL (NVIDIA Collective Communications Library)&lt;/strong&gt; implements &lt;strong&gt;collective operations&lt;/strong&gt;—&lt;strong&gt;all-reduce&lt;/strong&gt;, &lt;strong&gt;broadcast&lt;/strong&gt;, &lt;strong&gt;reduce-scatter&lt;/strong&gt;, &lt;strong&gt;all-gather&lt;/strong&gt;, and others—optimized for &lt;strong&gt;NVIDIA GPUs&lt;/strong&gt; across &lt;strong&gt;NVLink&lt;/strong&gt; within a node and &lt;strong&gt;RDMA&lt;/strong&gt; (&lt;strong&gt;InfiniBand&lt;/strong&gt; or &lt;strong&gt;RoCE&lt;/strong&gt;) across nodes. Its objective in &lt;strong&gt;AI&lt;/strong&gt; is to make &lt;strong&gt;distributed training&lt;/strong&gt; and multi-GPU &lt;strong&gt;inference&lt;/strong&gt; (tensor parallelism) scale: gradient shards must merge every step; attention and MLP partitions must exchange activations with minimal latency. Frameworks (&lt;strong&gt;PyTorch&lt;/strong&gt; DDP/FSDP, &lt;strong&gt;vLLM&lt;/strong&gt; tensor parallel) call NCCL (or delegate to it) rather than hand-rolling socket code.&lt;/p&gt;</description></item><item><title>RDMA (Remote Direct Memory Access)</title><link>https://lesitedefrancois.be/en/ai/rdma/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://lesitedefrancois.be/en/ai/rdma/</guid><description>&lt;p&gt;&lt;strong&gt;RDMA (Remote Direct Memory Access)&lt;/strong&gt; allows a network adapter to transfer data between the memory of two machines with &lt;strong&gt;little CPU overhead&lt;/strong&gt;, low latency, and often &lt;strong&gt;kernel bypass&lt;/strong&gt; (userspace stacks such as &lt;strong&gt;verbs&lt;/strong&gt; on InfiniBand or RoCE). Its objective in AI infrastructure is to keep &lt;strong&gt;GPUs&lt;/strong&gt; fed and synchronized: &lt;strong&gt;distributed training&lt;/strong&gt; exchanges gradients quickly, &lt;strong&gt;disaggregated inference&lt;/strong&gt; (&lt;strong&gt;llm-d&lt;/strong&gt;) moves &lt;strong&gt;KV cache&lt;/strong&gt; blocks between prefill and decode nodes, and &lt;strong&gt;NVMe-oF&lt;/strong&gt; storage delivers checkpoints without the host spending cycles copying every byte. &lt;strong&gt;DPUs&lt;/strong&gt; and &lt;strong&gt;SmartNICs&lt;/strong&gt; also use RDMA paths for storage and east-west traffic while the host CPU runs models.&lt;/p&gt;</description></item><item><title>RoCE (RDMA over Converged Ethernet)</title><link>https://lesitedefrancois.be/en/ai/roce/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://lesitedefrancois.be/en/ai/roce/</guid><description>&lt;p&gt;&lt;strong&gt;RoCE (RDMA over Converged Ethernet)&lt;/strong&gt; implements &lt;strong&gt;RDMA&lt;/strong&gt; semantics on &lt;strong&gt;Ethernet&lt;/strong&gt; (RoCEv2 uses UDP/IP), so NICs can perform remote memory access with low &lt;strong&gt;CPU&lt;/strong&gt; utilization over the same physical switches many enterprises already operate. Its objective is to deliver InfiniBand-like &lt;strong&gt;GPU&lt;/strong&gt; communication economics—fast &lt;strong&gt;NCCL&lt;/strong&gt; all-reduces, &lt;strong&gt;NVMe-oF&lt;/strong&gt;, &lt;strong&gt;llm-d&lt;/strong&gt; KV moves—without maintaining a separate InfiniBand fabric. RoCE requires &lt;strong&gt;lossless Ethernet&lt;/strong&gt; behavior: Priority Flow Control (&lt;strong&gt;PFC&lt;/strong&gt;), Explicit Congestion Notification (&lt;strong&gt;ECN&lt;/strong&gt;), buffer tuning, and often dedicated traffic classes so RDMA traffic is not dropped under burst load.&lt;/p&gt;</description></item></channel></rss>