<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Tensor-Parallelism on Le Site de François</title><link>https://lesitedefrancois.be/en/tags/tensor-parallelism/</link><description>Recent content in Tensor-Parallelism on Le Site de François</description><generator>Hugo -- gohugo.io</generator><language>en</language><copyright>© 2026 François</copyright><atom:link href="https://lesitedefrancois.be/en/tags/tensor-parallelism/index.xml" rel="self" type="application/rss+xml"/><item><title>NVLink</title><link>https://lesitedefrancois.be/en/ai/nvlink/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://lesitedefrancois.be/en/ai/nvlink/</guid><description>&lt;p&gt;&lt;strong&gt;NVLink&lt;/strong&gt; is NVIDIA’s proprietary &lt;strong&gt;high-speed interconnect&lt;/strong&gt; between GPUs (and, on some platforms, between GPUs and CPUs) inside a server or across an &lt;strong&gt;NVLink switch&lt;/strong&gt; system (e.g. NVL72-class racks). Its objective is to move tensors—activations, gradients, &lt;strong&gt;KV cache&lt;/strong&gt; shards, or partial attention results—at much higher bandwidth and lower latency than &lt;strong&gt;PCIe&lt;/strong&gt; or general &lt;strong&gt;Ethernet&lt;/strong&gt;, so multi-GPU &lt;strong&gt;training&lt;/strong&gt; and large-model &lt;strong&gt;inference&lt;/strong&gt; (tensor parallelism) are not bottlenecked on the bus. NVLink domains define which GPUs can treat each other’s memory as peer-accessible for &lt;strong&gt;CUDA&lt;/strong&gt; and &lt;strong&gt;NCCL&lt;/strong&gt; without leaving the box.&lt;/p&gt;</description></item></channel></rss>